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ISL6443A
Data Sheet December 7, 2007 FN6600.1
300kHz Dual, 180 Out-of-Phase, Step-Down PWM and Single Linear Controller
The ISL6443A is a high-performance, triple-output controller optimized for converting wall adapter, battery or network intermediate bus DC input supplies into the system supply voltages required for a wide variety of applications. Each output is adjustable down to 0.8V. The two PWMs are synchronized at 180 out of phase, thus reducing the RMS input current and ripple voltage. The ISL6443A incorporates several protection features. An adjustable overcurrent protection circuit monitors the output current by sensing the voltage drop across the lower MOSFET. Hiccup mode overcurrent operation protects the DC/DC components from damage during output overload/short circuit conditions. Each PWM has an independent logic-level shutdown input (SD1 and SD2). A single PGOOD signal is issued when soft-start is complete on both PWM controllers and their outputs are within 10% of the set point and the linear regulator output is greater than 75% of its setpoint. Thermal shutdown circuitry turns off the device if the junction temperature exceeds +150C.
Features
* Wide Input Supply Voltage Range - Variable 5.6V to 24V - Fixed 4.5V to 5.6V * Three Independently Programmable Output Voltages * Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . 300kHz * Out of Phase PWM Controller Operation - Reduces Required Input Capacitance and Power Supply Induced Loads * No External Current Sense Resistor - Uses Lower MOSFET's rDS(ON) * Bidirectional Frequency Synchronization for Synchronizing Multiple ISL6443As * Programmable Soft-Start * Extensive Circuit Protection Functions - PGOOD - UVLO - Overcurrent - Over-temperature - Independent Shutdown for Both PWMs * Excellent Dynamic Response - Voltage Feed-Forward with Current Mode Control * QFN Packages: - QFN - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Package Outline - Near Chip Scale Package Footprint, which Improves PCB Efficiency and has a Thinner Profile * Pb-Free (RoHS Compliant)
Ordering Information
PART NUMBER PART MARKING TEMP. RANGE (C) PACKAGE PKG. DWG. #
ISL6443AIRZ* 6443A IRZ (See Note) ISL6443AIVZ* 6443A IVZ (See Note)
-40 to +85 28 Ld 5x5 QFN L28.5x5 (Pb-free) -40 to +85 28 Ld TSSOP M28.173 (Pb-free)
Add "-TK" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Applications
* Power Supplies with Multiple Outputs * xDSL Modems/Routers * DSP, ASIC, and FPGA Power Supplies * Set-Top Boxes * Dual Output Supplies for DSP, Memory, Logic, P Core and I/O * Telecom Systems
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6443A Pinouts
ISL6443A (28 LD QFN) TOP VIEW
PHASE1 UGATE2 UGATE1 LGATE2 LGATE1 BOOT2 BOOT1
ISL6443A (28 LD TSSOP) TOP VIEW
LGATE2 1 BOOT2 2 UGATE2 3 21 ISEN1 20 PGND 19 SD1 18 SS1 17 SGND 16 OCSET1 15 FB1
28 LGATE1 27 BOOT1 26 UGATE1 25 PHASE1 24 ISEN1 23 PGND 22 SD1 21 SS1 20 SGND 19 OCSET1 18 FB1 17 SGND 16 GATE3 15 FB3
28 PHASE2 ISEN2 PGOOD VCC_5V SD2 SS2 OCSET2 1 2 3 4 5 6 7 8 FB2
27
26
25
24
23
22
PHASE2 4 ISEN2 5 PGOOD 6 VCC_5V 7 SD2 8 SS2 9 OCSET2 10 FB2 11 SGND 12 VIN 13 SYNC 14
9 SGND
10 VIN
11 SYNC
12 FB3
13 GATE3
14 SGND
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FN6600.1 December 7, 2007
Block Diagram
BOOT1 UGATE1 PHASE1 ADAPTIVE DEAD-TIME VCC_5V LGATE1 PGND V/I SAMPLE TIMING ADAPTIVE DEAD-TIME VCC_5V V/I SAMPLE TIMING LGATE2 PGOOD SD1 VIN SGND SD2 VCC_5V BOOT2 UGATE2 PHASE2
POR PGND ENABLE 0.8V REFERENCE BIAS SUPPLIES REFERENCE FAULT LATCH SOFT-START UV PGOOD UV PGOOD
3
GATE3
gm*VE
+
VE
+
-
FB3
ISL6443A
1400k FB1 180k
18.5pF
18.5pF
1400k
16k
OC1 OC2 PWM2
180k
VSEN2
+
+ 0.8V REF ERROR AMP 1
PWM1
16k
+ +
ERROR AMP 2
SOFT2
+
+ DUTY CYCLE RAMP GENERATOR PWM CHANNEL PHASE CONTROL
SS1 0.8V REF ISEN2
ISEN1
CURRENT SAMPLE
CURRENT SAMPLE CURRENT SAMPLE
+
+
CURRENT SAMPLE
OCSET1
OCSET2
+
1.7V REFERENCE
1.7V REFERENCE
+
+
FN6600.1 December 7, 2007
OC1
OC2
+
VIN SAME STATE FOR 2 CLOCK CYCLES REQUIRED TO LATCH OVERCURRENT FAULT
SYNC
VCC_5V SAME STATE FOR 2 CLOCK CYCLES REQUIRED TO LATCH OVERCURRENT FAULT
ISL6443A Typical Application Schematic
+12V + C2 4.7F VIN SS1 C4 0.1F C3 1F C7 0.1F BOOT1 18 10 VCC_5V 4 6 SS2 C5 0.1F BOOT2 C8 0.1F D2 BAT54HT1 C6 1F C1 56F
D1 BAT54HT1
24
27
UGATE1 23 PHASE1 22
28 1 2 ISL6443A (SEE NOTE)
UGATE2 PHASE2 ISEN2 R4 1.4k
VOUT1 +1.2V, 2A C9 + 330F
L1 6.4H
R3 1.4k
ISEN1
L2 6.4H + C10 330F R5 31.6k
21
VOUT2 +3.3V, 2A
LGATE1
Q1 FDS6990S
25 20 15
26 LGATE2 8 9 14 FB2 SGND SGND Q2 FDS6990S
R1 4.99k
PGND FB1
R2 10k
SD1 SD2 OCSET1
R6 10k C11 0.01F
19 5
13 GATE3 12 FB3 OCSET2 7 17 11 3 R8 120k PGOOD R9 10k VCC_5V V
VOUT2 +3.3V
16 R7 120k PGOOD SGND SYNC
R12 100
Q3 IRF7404
VOUT3 +2.5V, 500mA
R10 21.5k
C12 10F
R11 10k
NOTE: Pin numbers correspond to the QFN pinout.
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FN6600.1 December 7, 2007
ISL6443A
Absolute Maximum Ratings
Supply Voltage (VCC_5V Pin) . . . . . . . . . . . . . . . . . . . . -0.3V to +7V Input Voltage (VIN Pin). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+27V BOOT1, 2 and UGATE1, 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .+35V PHASE1, 2 and ISEN1, 2 . . . . . . . . . . . . . . . . . . . . .-5V (<100ns, 10J)/-0.3V (DC) to +27V BOOT1, 2 with Respect to PHASE1, 2 . . . . . . . . . . . . . . . . . . +6.5V UGATE1, 2. . . . . . . . . . . .(PHASE1, 2 - 0.3V) to (BOOT1, 2 + 0.3V) ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2000V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 28 Lead QFN (Notes 1, 2) . . . . . . . . 36 4 28 Lead TSSOP (Note 1) . . . . . . . . . 75 NA Maximum Junction Temperature . . . . . . . . . . . . . . .-55C to +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE: 1. JC is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. For JA the "case temp" location is the center of the exposed metal pad on the underside of the package. See Tech Brief TB379. 2. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to "Block Diagram" on page 3 and "Typical Application Schematic" on page 4. VIN = 5.6V to 24V, or VCC_5V = 5V 10%, TA = -40C to +85C (Note 6), Typical values are at TA = +25C. TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER VIN SUPPLY Input Voltage Range Input Voltage Range VCC_5V SUPPLY (Note 3) Input Voltage Output Voltage Maximum Output Current SUPPLY CURRENT Shutdown Current (Note 4) Operating Current (Note 5) REFERENCE SECTION Nominal Reference Voltage Reference Voltage Tolerance POWER-ON RESET Rising VCC_5V Threshold Falling VCC_5V Threshold OSCILLATOR Total Frequency Variation Peak-to-Peak Sawtooth Amplitude (Note 6)
5.6 VIN = VCC (Note 3) 4.5
12 5.0
24 5.6
V V
4.5 VIN > 5.6V, IL = 20mA VIN = 12V 4.5 60
5.0 5.0 -
5.6 5.5 -
V V mA
SD1 = SD2 = GND
-
50 2.0
375 4.0
A mA
-1.0
0.8 -
1.0
V %
4.25 3.95
4.45 4.2
4.5 4.4
V V
260 VIN = 12V VIN = 5V 4.16 3.5 -
300 1.6 0.667 1.0 5.0 4.8 -
340 5.44 1.5
kHz V V V ns MHz V V
Ramp Offset (Note 6) SYNC Input Rise/Fall Time (Note 6) SYNC Frequency Range SYNC Input HIGH Level SYNC Input LOW Level
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FN6600.1 December 7, 2007
ISL6443A
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to "Block Diagram" on page 3 and "Typical Application Schematic" on page 4. VIN = 5.6V to 24V, or VCC_5V = 5V 10%, TA = -40C to +85C (Note 6), Typical values are at TA = +25C. (Continued) TEST CONDITIONS MIN VCC - 0.6V TYP 15.0 MAX UNITS ns V
PARAMETER SYNC Input Minimum Pulse Width (Note 6) SYNC Output HIGH Level SHUTDOWN1/SHUTDOWN2 HIGH Level (Converter Enabled) LOW Level (Converter Disabled) PWM CONVERTERS Output Voltage FB Pin Bias Current Maximum Duty Cycle Minimum Duty Cycle PWM CONTROLLER ERROR AMPLIFIERS DC Gain (Note 6) Gain-Bandwidth Product (Note 6) Slew Rate (Note 6) PWM CONTROLLER GATE DRIVERS (Note 6) Sink/Source Current Upper Drive Pull-Up Resistance Upper Drive Pull-Down Resistance Lower Drive Pull-Up Resistance Lower Drive Pull-Down Resistance Rise Time Fall Time LINEAR CONTROLLER Drive Sink Current FB3 Feedback Threshold Undervoltage Threshold FB3 Input Leakage Current Amplifier Transconductance POWER GOOD AND CONTROL FUNCTIONS PGOOD LOW Level Voltage PGOOD Leakage Current PGOOD Upper Threshold, PWM 1 and 2 PGOOD Lower Threshold, PWM 1 and 2 PGOOD for Linear Controller ISEN AND CURRENT LIMIT Full Scale Input Current (Note 7) Overcurrent Threshold (Note 7) OCSET (Current Limit) Voltage
Internal Pull-up (3A)
2.0 -
-
0.8
V V
COUT = 1000pF, TA = +25C 93 -
0.8 4
150 -
V nA % %
-
88 15 2.0
-
dB MHz V/s
VCC_5V = 4.5V VCC_5V = 4.5V VCC_5V = 4.5V VCC_5V = 4.5V COUT = 1000pF COUT = 1000pF -
400 8 3.2 8 1.8 18 18
-
mA ns ns
50 I = 21mA VFB VFB = 0.8V, I = 21mA -
0.8 75 45 2
150 -
mA V % nA A/V
Pull-up = 100k
-
0.1 75
0.5 1.0 120 95 80
V A % % %
Fraction of set point Fraction of set point
105 80 70
ROCSET = 110k -
32 64 1.7
-
A A V
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FN6600.1 December 7, 2007
ISL6443A
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to "Block Diagram" on page 3 and "Typical Application Schematic" on page 4. VIN = 5.6V to 24V, or VCC_5V = 5V 10%, TA = -40C to +85C (Note 6), Typical values are at TA = +25C. (Continued) TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER SOFT-START Soft-Start Current PROTECTION Thermal Shutdown Rising
-
5
-
A
-
150 20
-
C C
Hysteresis NOTES:
3. In normal operation, where the device is supplied with voltage on the VIN pin, the VCC_5V pin provides a 5V output capable of 60mA (min). When the VCC_5V pin is used as a 5V supply input, the internal LDO regulator is disabled and the VIN input pin must be connected to the VCC_5V pin. (Refer to "Pin Descriptions" on page 10 for more details.) 4. This is the total shutdown current with VIN = VCC_5V = PVCC = 5V. 5. Operating current is the supply current consumed when the device is active but not switching. It does not include gate drive current. 6. Limits should be considered typical and are not production tested. 7. Established by characterization. The full scale current of 32A is recommended for optimum current sample and hold operation. See "Feedback Loop Compensation" on page 13.
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FN6600.1 December 7, 2007
ISL6443A Typical Performance Curves
(Oscilloscope Plots are Taken Using the ISL6443A EVAL Evaluation Board, VIN = 12V Unless Otherwise Noted.)
3.40 PWM1 OUTPUT VOLTAGE (V) PWM2 OUTPUT VOLTAGE (V) 3.39 3.38 3.37 3.36 3.35 3.34 3.33 3.32 3.31 3.30 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 LOAD CURRENT (A) 3.40 3.39 3.38 3.37 3.36 3.35 3.34 3.33 3.32 3.31 3.30 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 LOAD CURRENT (A)
FIGURE 1. PWM1 LOAD REGULATION
FIGURE 2. PWM2 LOAD REGULATION
PGOOD 5V/DIV 0.85 0.84 REFERENCE VOLTAGE (V) 0.83 0.82 0.81 0.80 0.79 0.78 0.77 0.76 0.75 -40 -20 20 40 0 TEMPERATURE (C) 60 80 VOUT1 2V/DIV VOUT2 2V/DIV VOUT3 2V/DIV
FIGURE 3. REFERENCE VOLTAGE VARIATION OVER TEMPERATURE
FIGURE 4. SOFT-START WAVEFORMS WITH PGOOD
VOUT1 20mV/DIV, AC-COUPLED
VOUT2 20mV/DIV, AC-COUPLED
IL1 0.5A/DIV, AC-COUPLED
IL2 0.5A/DIV, AC-COUPLED
PHASE1 10V/DIV
PHASE2 10V/DIV
FIGURE 5. PWM1 WAVEFORMS
FIGURE 6. PWM2 WAVEFORMS
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FN6600.1 December 7, 2007
ISL6443A Typical Performance Curves
(Continued)
(Oscilloscope Plots are Taken Using the ISL6443A EVAL Evaluation Board, VIN = 12V Unless Otherwise Noted.)
VOUT1 200mV/DIV AC-COUPLED
VOUT2 200mV/DIV AC-COUPLED
IOUT1 1A/DIV
IOUT2 1A/DIV
FIGURE 7. LOAD TRANSIENT RESPONSE VOUT1 (3.3V)
FIGURE 8. LOAD TRANSIENT RESPONSE VOUT2 (3.3V)
VCC_5V 1V/DIV
VOUT1 2V/DIV
IL1 2A/DIV
SS1 2V/DIV VOUT1 1V/DIV
FIGURE 9. PWM SOFT-START WAVEFORM
FIGURE 10. OVERCURRENT HICCUP MODE OPERATION
100
100
PWM1 EFFICIENCY (%)
PWM2 EFFICIENCY (%)
90
90
80
80
70
70
60 0 1 2 LOAD CURRENT (A) 3 4
60 0 1 2 LOAD CURRENT (A) 3 4
FIGURE 11. PWM1 EFFICIENCY vs LOAD (3.3V), VIN = 12V
FIGURE 12. PWM2 EFFICIENCY vs LOAD (3.3V), VIN = 12V
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FN6600.1 December 7, 2007
ISL6443A Pin Descriptions
BOOT2, BOOT1 - These pins power the upper MOSFET drivers of each PWM converter. Connect these pins to the junction of the bootstrap capacitor and the cathode of the bootstrap diode. The anode of the bootstrap diode is connected to the VCC_5V pin. UGATE2, UGATE1 - These pins provide the gate drive for the upper MOSFETs. PHASE2, PHASE1 - These pins are connected to the junction of the upper MOSFETs source, output filter inductor and lower MOSFETs drain. LGATE2, LGATE1 - These pins provide the gate drive for the lower MOSFETs. PGND - This pin provides the power ground connection for the lower gate drivers for both PWM1 and PWM2. This pin should be connected to the sources of the lower MOSFETs and the (-) terminals of the external input capacitors. FB3, FB2, FB1 - These pins are connected to the feedback resistor divider and provide the voltage feedback signals for the respective controller. They set the output voltage of the converter. In addition, the PGOOD circuit uses these inputs to monitor the output voltage status. ISEN2, ISEN1 - These pins are used to monitor the voltage drop across the lower MOSFET for current loop feedback and overcurrent protection. PGOOD - This is an open drain logic output used to indicate the status of the output voltages. This pin is pulled low when either of the two PWM outputs is not within 10% of the respective nominal voltage, or if the linear controller output is less than 75% of it's nominal value. Table 1 shows detailed status of PGOOD which can be classified into 4 cases under different combinations of SD1 and SD2 inputs. The first case is when both SD1 and SD2 are HIGH. PGOOD will be HIGH if all FB pins from the 3 REQUIRED outputs are within regulation AND soft-starts (SS1 AND SS2) are complete. The other two cases are when either of SD1 or SD2 is LOW which means the system wants to shut down one of the PWM outputs but still wants to keep another output working. PGOOD will be HIGH if all the FB pins from the 2
TABLE 1. SD1 1 1 0 0 SD2 1 0 1 0 LDO > 75%? Y Y Y x 90% < FB1 < 110%? 90% < FB2 < 110%? SS1 COMPLETED? SS2 COMPLETED? Y Y x x Y x Y x Y Y x x Y x Y x PGOOD 1 1 1 0
REQUIRED outputs are within regulation AND soft-start (SS1/SS2) is complete. The last case is when both of the SD1 and SD2 are LOW. PGOOD will be low. SGND - (Pin 20 on the TSSOP; Pin 17 on the QFN) This is the small-signal ground, common to all 3 controllers, and must be routed separately from the high current ground (PGND). All voltage levels are measured with respect to this pin. Connect the additional SGND pins to this pin. If using a 5V supply, connect this pin to VCC_5V. A small ceramic capacitor should be connected right next to this pin for noise decoupling. VIN - Use this pin to power the device with an external supply voltage with a range of 5.6V to 24V. For 5V 10% operation, connect this pin to VCC_5V. VCC_5V - This pin is the output of the internal 5V linear regulator. This output supplies the bias for the IC, the low side gate drivers, and the external boot circuitry for the high side gate drivers. The IC may be powered directly from a single 5V (10%) supply at this pin. When used as a 5V supply input, this pin must be externally connected to VIN. The VCC_5V pin must be always de-coupled to power ground with a minimum of 4.7F ceramic capacitor, placed very close to the pin. SYNC - This pin may be used to synchronize two or more ISL6443A controllers. This pin requires a 1k resistor to ground if used; connect directly to VCC_5V if not used. SS1, SS2 - These pins provide a soft-start function for their respective PWM controllers. When the chip is enabled, the regulated 5A pull-up current source charges the capacitor connected from this pin to ground. The error amplifier reference voltage ramps from 0V to 0.8V while the voltage on the soft-start pin ramps from 0V to 0.8V. SD1, SD2 - These pins provide an enable/disable function for their respective PWM output. The output is enabled when this pin is floating or pulled HIGH, and disabled when the pin is pulled LOW. GATE3 - This pin is the open drain output of the linear regulator controller. OCSET2, OCSET1 - A resistor from this pin to ground sets the overcurrent threshold for the respective PWM.
"x" means "don't care".
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FN6600.1 December 7, 2007
ISL6443A Functional Description
General Description
The ISL6443A integrates control circuits for two synchronous buck converters and one linear controller. The two synchronous bucks operate out-of-phase to substantially reduce the input ripple and thus reduce the input filter requirements. The chip has four control lines (SS1, SD1, SS2, and SD2), which provide independent control for each of the synchronous buck outputs. The buck PWM controllers employ a free-running frequency of 300kHz. The current mode control scheme with an input voltage feed-forward ramp input to the modulator provides excellent rejection of input voltage variations and provides simplified loop compensations. The linear controller can drive either a PNP or PFET to provide ultra low-dropout regulation with programmable voltages. main outputs at start-up. The soft-start time can be obtained from Equation 1:
C SS t SOFT = 0.8V ----------- 5A (EQ. 1)
VCC_5V 1V/DIV
VOUT1 1V/DIV
SS1 1V/DIV
Internal 5V Linear Regulator (VCC_5V)
All ISL6443A functions are internally powered from an on-chip, low dropout 5V regulator. The maximum regulator input voltage is 24V. Bypass the regulator's output (VCC_5V) with a 4.7F capacitor to ground. The dropout voltage for this LDO is typically 600mV, so when VIN is greater than 5.6V, VCC_5V is typically 5V. The ISL6443A also employs an undervoltage lockout circuit that disables both regulators when VCC_5V falls below 4.4V. The internal LDO can source over 60mA to supply the IC, power the low side gate drivers and charge the external boot capacitor. When driving large FETs (especially at 300kHz frequency), little or no regulator current may be available for external loads. For example, a single large FET with 15nC total gate charge requires 15nC x 300kHz = 4.5mA. Also, at higher input voltages with larger FETs, the power dissipation across the internal 5V will increase. Excessive dissipation across this regulator must be avoided to prevent the junction temperature from rising. Larger FETs can be used with 5V 10% input applications. The thermal overload protection circuit will be triggered if the VCC_5V output is short circuited. Connect VCC_5V to VIN for 5V 10% input applications.
FIGURE 13. SOFT-START OPERATION
The soft-start capacitors can be chosen to provide start-up tracking for the two PWM outputs. This can be achieved by choosing the soft-start capacitors such that the soft-start capacitor ratio equals the respective PWM output voltage ratio. For example, if one uses PWM1 = 1.2V and PWM2 = 3.3V, then the soft-start capacitor ratio should be, CSS1/CSS2 = 1.2/3.3 = 0.364. Figure 14 shows that soft-start waveform with CSS1 = 0.01F and CSS2 = 0.027F.
VOUT2 1V/DIV
VOUT1 1V/DIV
Soft-Start Operation
When soft-start is initiated, the voltage on the SS pin of the enabled PWM channels starts to ramp gradually, due to the 5A current sourced into the external capacitor. The output voltage follows the soft-start voltage. When the SS pin voltage reaches 0.8V, the output voltage of the enabled PWM channel reaches the regulation point, and the soft-start pin voltage continues to rise. At this point the PGOOD and fault circuitry is enabled. This completes the soft-start sequence. Any further rise of SS pin voltage does not affect the output voltage. By varying the values of the soft-start capacitors, it is possible to provide sequencing of the
FIGURE 14. PWM1 AND PWM2 OUTPUT TRACKING DURING START-UP
Output Voltage Programming
A resistive divider from the output to ground sets the output voltage of either PWM channel. The center point of the divider shall be connected to FBx pin. The output voltage value is determined by Equation 2.
R 1 + R 2 V OUTx = 0.8V -------------------- R2 (EQ. 2)
where R1 is the top resistor of the feedback divider network and R2 is the resistor connected from FBx to ground.
FN6600.1 December 7, 2007
11
ISL6443A
Out-of-Phase Operation
The two PWM controllers in the ISL6443A operate out-of-phase to reduce input ripple current. This reduces the input capacitor ripple current requirements, reduces power supply-induced noise and improves EMI. This effectively helps to lower component cost, save board space and reduce EMI. Dual PWMs typically operate in-phase and turn on both upper FETs at the same time. The input capacitor must then support the instantaneous current requirements of both controllers simultaneously, resulting in increased ripple voltage and current. The higher RMS ripple current lowers the efficiency due to the power loss associated with the ESR of the input capacitor. This typically requires more low-ESR capacitors in parallel to minimize the input voltage ripple and ESR-related losses, or to meet the required ripple current rating. With dual synchronized out-of-phase operation, the high-side MOSFETs of the ISL6443A turn on 180o out-of-phase. The instantaneous input current peaks of both regulators no longer overlap, resulting in reduced RMS ripple current and input voltage ripple. This reduces the required input capacitor ripple current rating, allowing fewer or less expensive capacitors, and reducing the shielding requirements for EMI. The "Typical Performance Curves" on page 8 show the synchronized 180 out-of-phase operation. 180o MOSFETs. Shoot-through control logic provides a 20ns deadtime to ensure that both the upper and lower MOSFETs will not turn on simultaneously and cause a shoot-through condition.
Gate Drivers
The low-side gate driver is supplied from VCC_5V and provides a peak sink/source current of 400mA. The high-side gate driver is also capable of 400mA current. Gate-drive voltages for the upper N-Channel MOSFET are generated by the flying capacitor boot circuit. A boot capacitor connected from the BOOT pin to the PHASE node provides power to the high side MOSFET driver. To limit the peak current in the IC, an external resistor may be placed between the UGATE pin and the gate of the external MOSFET. This small series resistor also damps any oscillations caused by the resonant tank of the parasitic inductances in the traces of the board and the FET's input capacitance.
VIN
VCC_5V
BOOT UGATE PHASE
Input Voltage Range
The ISL6443A is designed to operate from input supplies ranging from 4.5V to 24V. However, the input voltage range can be effectively limited by the available maximum duty cycle (DMAX = 93%).
V OUT + V d1 V IN ( min ) = -------------------------------- + V d2 - V d1 0.93 (EQ. 3)
ISL6443A
FIGURE 15.
where, Vd1 = Sum of the parasitic voltage drops in the inductor discharge path, including the lower FET, inductor and PC board. Vd2 = Sum of the voltage drops in the charging path, including the upper FET, inductor and PC board resistances. The maximum input voltage and minimum output voltage is limited by the minimum on-time (tON(min)).
V OUT V IN ( max ) --------------------------------------------------t ON ( min ) x 300kHz (EQ. 4)
At start-up, the low-side MOSFET turns on and forces PHASE to ground in order to charge the BOOT capacitor to 5V. After the low-side MOSFET turns off, the high-side MOSFET is turned on by closing an internal switch between BOOT and UGATE. This provides the necessary gate-to-source voltage to turn on the upper MOSFET, an action that boosts the 5V gate drive signal above VIN. The current required to drive the upper MOSFET is drawn from the internal 5V regulator.
Protection Circuits
The converter output is monitored and protected against overload, short circuit and undervoltage conditions. A sustained overload on the output sets the PGOOD low and initiates hiccup mode.
where, tON(min) = 30ns
Gate Control Logic
The gate control logic translates generated PWM signals into gate drive signals, which provides amplification, level shifting and shoot-through protection. The gate drivers have some circuitry that helps optimize the ICs performance over a wide range of operational conditions. As MOSFET switching times can vary dramatically from type to type and with input voltage, the gate control logic provides adaptive dead time by monitoring real gate waveforms of both the upper and the lower 12
Overcurrent Protection
Both PWM controllers use the lower MOSFET's on-resistance, rDS(ON) , to monitor the current in the converter. The sensed voltage drop is compared with a threshold set by a resistor connected from the OCSETx pin to ground.
( 7 ) ( R CS ) R OCSET = ---------------------------------------( I OC ) ( r DS ( on ) ) (EQ. 5)
FN6600.1 December 7, 2007
ISL6443A
where, IOC is the desired overcurrent protection threshold, and RCS is a value of the current sense resistor connected to the ISENx pin. If an overcurrent is detected for 2 consecutive clock cycles, then the IC enters a hiccup mode by turning off the gate drivers and entering into soft-start. The IC will cycle 2 times through soft-start before trying to restart. The IC will continue to cycle through soft-start until the overcurrent condition is removed. Hiccup mode is active during soft-start, so care must be taken to ensure that the peak inductor current does not exceed the overcurrent threshold during soft-start. Because of the nature of this current sensing technique, and to accommodate a wide range of rDS(ON) variations, the value of the overcurrent threshold should represent an overload current about 150% to 180% of the maximum operating current. If more accurate current protection is desired, place a current sense resistor in series with the lower MOSFET source.
Feedback Loop Compensation
To reduce the number of external components and to simplify the process of determining compensation components, both PWM controllers have internally compensated error amplifiers. To make internal compensation possible, several design measures were taken. First, the ramp signal applied to the PWM comparator is proportional to the input voltage provided via the VIN pin. This keeps the modulator gain constant with variation in the input voltage. Second, the load current proportional signal is derived from the voltage drop across the lower MOSFET during the PWM time interval and is subtracted from the amplified error signal on the comparator input. This creates an internal current control loop. The resistor connected to the ISEN pin sets the gain in the current feedback loop. Equation 6 estimates the required value of the current sense resistor depending on the maximum operating load current and the value of the MOSFET's rDS(ON).
( I MAX ) ( r DS ( ON ) ) R CS ---------------------------------------------32A (EQ. 6)
Over-Temperature Protection
The IC incorporates an over-temperature protection circuit that shuts the IC down when a die temperature of +150C is reached. Normal operation resumes when the die temperatures drops below +130C through the initiation of a full soft-start cycle.
Choosing RCS to provide 32A of current to the current sample and hold circuitry is recommended but values down to 2A and up to 100A can be used. Due to the current loop feedback, the modulator has a single pole response with -20dB slope at a frequency determined by the load.
1 F PO = -------------------------------2 R O C O (EQ. 7)
Implementing Synchronization
The SYNC pin may be used to synchronize two or more controllers. When the SYNC pins of two controllers are connected together, one controller becomes the master and the other controller synchronizes to the master. A pull-down resistor is required and must be sized to provide a low enough time constant to pass the SYNC pulse. Connect this pin to VCC_5V if not used. Figure 16 shows the SYNC pin waveform operating at 16 times the switching frequency.
where RO is load resistance and CO is load capacitance. For this type of modulator, a Type 2 compensation circuit is usually sufficient. Figure 17 shows a Type 2 amplifier and its response along with the responses of the current mode modulator and the converter. The Type 2 amplifier, in addition to the pole at origin, has a zero-pole pair that causes a flat gain region at frequencies in between the zero and the pole.
1 F Z = ------------------------------ = 6kHz 2 R 2 C 1 1 F P = ------------------------------ = 600kHz 2 R 1 C 2 (EQ. 8)
(EQ. 9)
FIGURE 16. SYNC WAVEFORM
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ISL6443A
C2 R2 CONVERTER R1 EA TYPE 2 EA GM = 17.5dB
MODULATOR
C1
rise above its set point. Care must be taken to ensure that the feedback resistor's current exceeds the pass transistors leakage current over the entire temperature range. The linear regulator output can be supplied by the output of one of the PWMs. When using a PFET, the output of the linear regulator will track the PWM supply after the PWM output rises to a voltage greater than the threshold of the PFET pass device. The voltage differential between the PWM and the linear output will be the load current times the rDS(ON). Figure 18 shows the linear regulator (2.5V) start-up waveform and the PWM (3.3V) start-up waveform.
GEA = 18dB FZ FP FC
FPO
FIGURE 17. FEEDBACK LOOP COMPENSATION
VOUT2 1V/DIV
The zero frequency, the amplifier high-frequency gain, and the modulator gain are chosen to satisfy most typical applications. The crossover frequency will appear at the point where the modulator attenuation equals the amplifier high frequency gain. The only task that the system designer has to complete is to specify the output filter capacitors to position the load main pole somewhere within one decade lower than the amplifier zero frequency. With this type of compensation plenty of phase margin is easily achieved due to zero-pole pair phase `boost'. Conditional stability may occur only when the main load pole is positioned too much to the left side on the frequency axis due to excessive output filter capacitance. In this case, the ESR zero placed within the 1.2kHz to 30kHz range gives some additional phase `boost'. Some phase boost can also be achieved by connecting capacitor CZ in parallel with the upper resistor R1 of the divider that sets the output voltage value. Please refer to "Output Inductor Selection" and "Output Capacitor Selection" on page 16 for further details.
VOUT3 1V/DIV
FIGURE 18. LINEAR REGULATOR START-UP WAVEFORM
60 50 40 30 20 10 0 0.79
Linear Regulator
The linear regulator controller is a transconductance amplifier with a nominal gain of 2A/V. The N-Channel MOSFET output device can sink a minimum of 50mA. The reference voltage is 0.8V. With 0V differential at it's input, the controller sinks 21mA of current. An external PNP transistor or PFET pass element can be used. The dominant pole for the loop can be placed at the base of the PNP (or gate of the PFET), as a capacitor from emitter to base (source to gate of a PFET). Better load transient response is achieved, however, if the dominant pole is placed at the output, with a capacitor to ground at the output of the regulator. Under no-load conditions, leakage currents from the pass transistors supply the output capacitors, even when the transistor is off. Generally this is not a problem since the feedback resistor drains the excess charge. However, charge may build up on the output capacitor making VLDO
ERROR AMPLIFIER SINK CURRENT (mA)
0.80
0.82 0.83 0.81 FEEDBACK VOLTAGE (V)
0.84
0.85
FIGURE 19. LINEAR CONTROLLER GAIN
Base-Drive Noise Reduction
The high-impedance base driver is susceptible to system noise, especially when the linear regulator is lightly loaded. Capacitively coupled switching noise or inductively coupled EMI onto the base drive causes fluctuations in the base current, which appear as noise on the linear regulator's output. Keep the base drive traces away from the step-down converter, and as short as possible, to minimize noise
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ISL6443A
coupling. A resistor in series with the gate drivers reduces the switching noise generated by PWM. Additionally, a bypass capacitor may be placed across the base-to-emitter resistor. This bypass capacitor, in addition to the transistor's input capacitor, could bring in a second pole that will destabilize the linear regulator. Therefore, the stability requirements determine the maximum base-to-emitter capacitance. 6. Place VCC_5V bypass capacitor very close to VCC_5V pin of the IC and connect its ground to the PGND plane. 7. Place the gate drive components BOOT diode and BOOT capacitors together near controller IC 8. The output capacitors should be placed as close to the load as possible. Use short wide copper regions to connect output capacitors to load to avoid inductance and resistances. 9. Use copper filled polygons or wide but short trace to connect the junction of upper FET, lower FET and output inductor. Also keep the PHASE node connection to the IC short. It is unnecessary to oversize the copper islands for PHASE node. Since the phase nodes are subjected to very high dv/dt voltages, the stray capacitor formed between these islands and the surrounding circuitry will tend to couple switching noise. 10. Route all high speed switching nodes away from the control circuitry. 11. Create a separate small analog ground plane near the IC. Connect the SGND pin to this plane. All small signal grounding paths, including feedback resistors, current limit setting resistors, and SYNC/SDx pull-down resistors should be connected to this SGND plane. 12. Ensure the feedback connection to the output capacitor is short and direct.
Layout Guidelines
Careful attention to layout requirements is necessary for successful implementation of a ISL6443A based DC/DC converter. The ISL6443A switches at a very high frequency and therefore the switching times are very short. At these switching frequencies, even the shortest trace has significant impedance. Also the peak gate drive current rises significantly in extremely short time. Transition speed of the current from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, generate EMI, increase device overvoltage stress and ringing. Careful component selection and proper PC board layout minimizes the magnitude of these voltage spikes. There are two sets of critical components in a DC/DC converter using the ISL6443A. The switching power components and the small signal components. The switching power components are the most critical from a layout point of view because they switch a large amount of energy so they tend to generate a large amount of noise. The critical small signal components are those connected to sensitive nodes or those supplying critical bias currents. A multi-layer printed circuit board is recommended.
Component Selection Guidelines
MOSFET Considerations
The logic level MOSFETs are chosen for optimum efficiency given the potentially wide input voltage range and output power requirements. Two N-Channel MOSFETs are used in each of the synchronous-rectified buck converters for the PWM1 and PWM2 outputs. These MOSFETs should be selected based upon rDS(ON), gate supply requirements, and thermal management considerations. The power dissipation includes two loss components; conduction loss and switching loss. These losses are distributed between the upper and lower MOSFETs according to duty cycle (see the following equations). The conduction losses are the main component of power dissipation for the lower MOSFETs. Only the upper MOSFET has significant switching losses, since the lower device turns on and off into near zero voltage. The equations assume linear voltage-current transitions and do not model power loss due to the reverse-recovery of the lower MOSFET's body diode.
( I O ) ( r DS ( ON ) ) ( V OUT ) ( I O ) ( V IN ) ( t SW ) ( F SW ) P UPPER = -------------------------------------------------------------- + ----------------------------------------------------------V IN 2 (EQ.10) ( I O ) ( r DS ( ON ) ) ( V IN - V OUT ) P LOWER = -----------------------------------------------------------------------------V IN
2 2
Layout Considerations
1. The Input capacitors, Upper FET, Lower FET, Inductor and Output capacitor should be placed first. Isolate these power components on the topside of the board with their ground terminals adjacent to one another. Place the input high frequency decoupling ceramic capacitor very close to the MOSFETs. 2. Use separate ground planes for power ground and small signal ground. Connect the SGND and PGND together close to the IC. Do not connect them together anywhere else. 3. The loop formed by Input capacitor, the top FET and the bottom FET must be kept as small as possible. 4. Ensure the current paths from the input capacitor to the MOSFET, to the output inductor and output capacitor are as short as possible with maximum allowable trace widths. 5. Place The PWM controller IC close to lower FET. The LGATE connection should be short and wide. The IC can be best placed over a quiet ground area. Avoid switching ground loop current in this area.
(EQ.11)
A large gate-charge increases the switching time, tSW, which increases the upper MOSFET switching losses. Ensure that both MOSFETs are within their maximum
FN6600.1 December 7, 2007
15
ISL6443A
junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. components. Consult with the manufacturer of the load circuitry for specific decoupling requirements. Use only specialized low-ESR capacitors intended for switching-regulator applications at 300kHz for the bulk capacitors. In most cases, multiple small-case electrolytic capacitors perform better than a single large-case capacitor. The stability requirement on the selection of the output capacitor is that the `ESR zero' (f Z) be between 1.2kHz and 30kHz. This range is set by an internal, single compensation zero at 6kHz. The ESR zero can be a factor of five on either side of the internal zero and still contribute to increased phase margin of the control loop. Therefore,
1 C OUT = -----------------------------------2 ( ESR ) ( f Z ) (EQ.14)
Output Capacitor Selection
The output capacitors for each output have unique requirements. In general, the output capacitors should be selected to meet the dynamic regulation requirements including ripple voltage and load transients. Selection of output capacitors is also dependent on the output inductor, so some inductor analysis is required to select the output capacitors. One of the parameters limiting the converter's response to a load transient is the time required for the inductor current to slew to it's new level. The ISL6443A will provide either 0% or 71% duty cycle in response to a load transient. The response time is the time interval required to slew the inductor current from an initial current value to the load current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor(s). Minimizing the response time can minimize the output capacitance required. Also, if the load transient rise time is slower than the inductor response time, as in a hard drive or CD drive, it reduces the requirement on the output capacitor. The maximum capacitor value required to provide the full, rising step, transient load current during the response time of the inductor is:
( L O ) ( I TRAN ) C OUT = ---------------------------------------------------------2 ( V IN - V O ) ( DV OUT )
2
In conclusion, the output capacitors must meet three criteria: 1. They must have sufficient bulk capacitance to sustain the output voltage during a load transient while the output inductor current is slewing to the value of the load transient. 2. The ESR must be sufficiently low to meet the desired output voltage ripple due to the output inductor current. 3. The ESR zero should be placed, in a rather large range, to provide additional phase margin. The recommended output capacitor value for the ISL6443A is between 150F to 680F, to meet stability criteria with external compensation. Use of aluminum electrolytic, POSCAP, or tantalum type capacitors is recommended. Use of low ESR ceramic capacitors is possible but would take more rigorous loop analysis to ensure stability.
(EQ. 12)
where, COUT is the output capacitor(s) required, LO is the output inductor, ITRAN is the transient load current step, VIN is the input voltage, VO is output voltage, and DVOUT is the drop in output voltage allowed during the load transient. High frequency capacitors initially supply the transient current and slow the load rate-of-change seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (Equivalent Series Resistance) and voltage rating requirements as well as actual capacitance requirements. The output voltage ripple is due to the inductor ripple current and the ESR of the output capacitors as defined by Equation 13:
V RIPPLE = I L ( ESR ) (EQ.13)
Output Inductor Selection
The PWM converters require output inductors. The output inductor is selected to meet the output voltage ripple requirements. The inductor value determines the converter's ripple current and the ripple voltage is a function of the ripple current and output capacitor(s) ESR. The ripple voltage expression is given in "Output Capacitor Selection" on page 16 and the ripple current is approximated by Equation 15:
( V IN - V OUT ) ( V OUT ) I L = --------------------------------------------------------( f S ) ( L ) ( V IN ) (EQ. 15)
For the ISL6443A, inductor values between 6.4H to 10H are recommended when using the "Typical Application Schematic" on page 4. Other values can be used but a thorough stability study should be done.
where, IL is calculated in "Output Inductor Selection" on page 16. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance
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ISL6443A
Input Capacitor Selection
The important parameters for the bulk input capacitor(s) are the voltage rating and the RMS current rating. For reliable operation, select bulk input capacitors with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and 1.5 times is a conservative guideline. The AC RMS Input current varies with the load. The total RMS current supplied by the input capacitance is:
I RMS = I RMS1 + I RMS2
2 2 5.0 4.5 4.0 INPUT RMS CURRENT 3.5 3.0 2.5 2.0 1.5 1.0 3.3V 5V OUT-OF-PHASE IN-PHASE
(EQ.16)
0.5 0 0 1 2 3 3.3V AND 5V LOAD CURRENT 4 5
where,
I RMSx = DC - DC I O
2
(EQ.17)
FIGURE 20. INPUT RMS CURRENT vs LOAD
DC is duty cycle of the respective PWM. Depending on the specifics of the input power and its impedance, most (or all) of this current is supplied by the input capacitor(s). Figure 20 shows the advantage of having the PWM converters operating out-of-phase. If the converters were operating in-phase, the combined RMS current would be the algebraic sum, which is a much larger value as shown. The combined out-of-phase current is the square root of the sum of the square of the individual reflected currents and is significantly less than the combined in-phase current.
Use a mix of input bypass capacitors to control the voltage ripple across the MOSFETs. Use ceramic capacitors for the high frequency decoupling and bulk capacitors to supply the RMS current. Small ceramic capacitors can be placed very close to the upper MOSFET to suppress the voltage induced in the parasitic circuit impedances. For board designs that allow through-hole components, the Sanyo OS-CON(R) series offer low ESR and good temperature performance. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. The TPS series available from AVX is surge-current tested.
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ISL6443A
Package Outline Drawing
L28.5x5
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 10/07
4X 3.0 5.00 A B 6 PIN 1 INDEX AREA 24X 0.50 6 PIN #1 INDEX AREA
22
28 1
21
5.00
3 .10 0 . 15
15
(4X) 0.15 14 8
7
TOP VIEW
28X 0.55 0.10
0.10 M C A B - 0.07 4 28X 0.25 + 0.05
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 0.1 BASE PLANE ( 4. 65 TYP ) ( 24X 0 . 50) ( 3. 10)
C
SEATING PLANE 0.08 C
SIDE VIEW
(28X 0 . 25 ) C 0 . 2 REF 5
( 28X 0 . 75)
0 . 00 MIN. 0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
18
FN6600.1 December 7, 2007
ISL6443A Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 L 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 GAUGE PLANE 0.25(0.010) M BM
M28.173
28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.031 0.0075 0.0035 0.378 0.169 MAX 0.047 0.006 0.051 0.0118 0.0079 0.386 0.177 MILLIMETERS MIN 0.05 0.80 0.19 0.09 9.60 4.30 MAX 1.20 0.15 1.05 0.30 0.20 9.80 4.50 NOTES 9 3 4 6 7 8o Rev. 0 6/98
A1 0.10(0.004) A2 c
e
b 0.10(0.004) M C AM BS
E1 e E L N
0.026 BSC 0.246 0.0177 28 0o 8o 0.256 0.0295
0.65 BSC 6.25 0.45 28 0o 6.50 0.75
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AE, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN6600.1 December 7, 2007

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